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How an idea becomes a chip

What happens when someone decides to build a chip? Follow the journey from a product idea all the way to a tested device — twelve connected stages, each linked to the concepts and processes behind it. Flows vary by chip type (digital, analog, memory, RF) and by company, so treat this as the shape of the journey rather than a rigid recipe.

  1. Design

    Define the problem

    Design

    What should this chip do — and for whom?

    What happens
    A market or product need is turned into concrete requirements: functions, performance, power, area, cost, and the interfaces the chip must support.
    Why it's needed
    Every later decision is judged against these requirements. A vague specification leads to a chip that works but does not fit the product.
    Who does it
    Product managers, system architects, and customers.
    What can go wrong
    Missing or ambiguous requirements, or targets that are physically or economically impossible.
    Goes in
    Market need, use cases, and constraints (cost, power budget, schedule).
    Comes out
    A product and technical specification.

  2. Create the architecture

    Design

    How will the chip be organised to meet the spec?

    What happens
    Architects choose the major blocks (CPU/GPU/accelerators, memory, I/O), how they connect, and the performance–power–area trade-offs — the microarchitecture.
    Why it's needed
    The architecture sets the ceiling on performance and efficiency before a single line of RTL is written.
    Who does it
    Chip and system architects.
    What can go wrong
    Over- or under-designing, or baking in bottlenecks such as memory bandwidth or interconnect limits.
    Goes in
    The specification.
    Comes out
    An architecture / microarchitecture definition and block diagram.
    Learn thisArchitecture →Integrated circuit →

  3. Design the logic

    Design

    What digital logic implements each block?

    What happens
    Blocks are expressed as Boolean logic and functional units — datapaths, control, and state machines — built from logic gates and standard cells.
    Why it's needed
    Logic is the bridge between architectural intent and something that can be described in hardware.
    Who does it
    Digital design engineers.
    What can go wrong
    Logic that is correct but too slow, too large, or too power-hungry.
    Goes in
    The architecture / microarchitecture.
    Comes out
    A functional logic definition.
    Learn thisLogic →CMOS →MOSFET →

  4. Write RTL

    Design

    How is the logic captured in a hardware language?

    What happens
    Engineers describe the design at register-transfer level in a hardware description language (e.g. Verilog/SystemVerilog): registers and the logic between them, evaluated each clock cycle.
    Why it's needed
    RTL is the human-written, machine-readable source that tools transform into a physical chip.
    Who does it
    RTL / design engineers.
    What can go wrong
    Functional bugs, untestable code, or RTL that cannot meet timing after synthesis.
    Goes in
    Logic design and specification.
    Comes out
    Synthesizable RTL plus timing and design constraints.
    Learn thisRTL →

  5. Verify the design

    Design

    Does the design actually do what the spec says?

    What happens
    The RTL is exercised with simulation, testbenches, assertions, and coverage — and sometimes formal methods — to find bugs before anything is manufactured.
    Why it's needed
    Fixing a bug in RTL costs minutes; finding it after tape-out can cost months and a costly mask respin.
    Who does it
    Verification engineers — often the largest team on a project.
    What can go wrong
    Missed corner cases — a bug that escapes to silicon.
    Goes in
    RTL and a verification plan.
    Comes out
    Verified RTL with coverage evidence and a closed bug list.
    Learn thisVerification →

  6. Synthesize

    Design

    How does RTL become a gate-level circuit?

    What happens
    A synthesis tool maps RTL onto a foundry's standard-cell library for a target process, optimising for timing, area, and power under the given constraints.
    Why it's needed
    It translates abstract code into the actual gates the foundry can build.
    Who does it
    Implementation engineers using EDA (electronic design automation) tools.
    What can go wrong
    Timing not met, area or power blow-up, or constraints that do not reflect reality.
    Goes in
    RTL, constraints, and a standard-cell library from the foundry's PDK.
    Comes out
    A gate-level netlist.
    Learn thisSynthesis →CMOS (standard cells) →

  7. Design the physical layout

    Design

    Where does every gate and wire physically go on the die?

    What happens
    Floorplanning, placement, clock-tree synthesis, and routing turn the netlist into an actual geometric layout of cells and interconnect.
    Why it's needed
    Physics — distance, resistance, capacitance — decides real speed and power, not the netlist alone.
    Who does it
    Physical-design / implementation engineers.
    What can go wrong
    Routing congestion, timing or IR-drop problems, or a layout that cannot close.
    Goes in
    Gate-level netlist, constraints, and the PDK.
    Comes out
    A placed-and-routed layout.
    Learn thisPhysical design →Place & route →

  8. Sign off

    Design

    Is the layout correct, manufacturable, and reliable?

    What happens
    Final checks — static timing analysis (STA), design-rule check (DRC), layout-versus-schematic (LVS), IR-drop, and electromigration/reliability — confirm the design is ready.
    Why it's needed
    These are the last gates before committing to expensive masks and fabrication.
    Who does it
    Signoff and CAD engineers.
    What can go wrong
    A violation slipping through, or margins that are too optimistic.
    Goes in
    The final layout and the foundry's rule decks.
    Comes out
    A clean, signed-off design database.
    Learn thisSignoff →

  9. Tape out

    Design

    What is handed to the foundry?

    What happens
    The finished layout is packaged as a database (e.g. GDSII/OASIS) and sent to the foundry to make the photomasks — the point of no return.
    Why it's needed
    It is the formal hand-off from design to manufacturing.
    Who does it
    The design team, handing off to the foundry.
    What can go wrong
    A late error becomes an expensive mask respin and schedule slip.
    Goes in
    The signed-off design database.
    Comes out
    A mask data set at the foundry.
    Learn thisTapeout →

  10. Manufacture

    Manufacture

    Manufacture

    How is the chip actually built on silicon?

    What happens
    In the fab, hundreds of steps — lithography, deposition, etching, doping, CMP, and metallization — build the design layer by layer on a silicon wafer.
    Why it's needed
    This is where the design becomes physical transistors and wires.
    Who does it
    Fab process engineers and operators (a foundry or an IDM).
    What can go wrong
    Defects and process variation that reduce yield.
    Goes in
    Photomasks and blank wafers.
    Comes out
    Finished wafers, each holding many dies.
    Learn thisPhotolithography →Etching and Deposition →Deposition →Manufacturing process explorer →

  11. Package

    Package

    Package

    How does the tiny die connect to the outside world?

    What happens
    Wafers are diced into individual dies, which are attached to a package or substrate and connected — by wire bond, flip-chip, or advanced 2.5D/3D methods — then encapsulated.
    Why it's needed
    Packaging provides electrical connections, mechanical protection, and a thermal path — and increasingly sets overall system performance.
    Who does it
    OSATs, foundry advanced-packaging lines, or IDMs.
    What can go wrong
    Thermal, warpage, and interconnect-reliability problems.
    Goes in
    Tested wafers and dies.
    Comes out
    Packaged chips.
    Learn thisDicing →Chip Packaging →Traditional packaging →Flip chip →

  12. Test

    Test

    Test

    Does each finished chip actually work?

    What happens
    Chips are tested — at wafer level and again after packaging (final test) — for function, speed, and reliability, then binned or discarded.
    Why it's needed
    Only known-good chips should reach customers, and the test data also feeds yield learning back to design and the fab.
    Who does it
    Test and product engineers.
    What can go wrong
    Test escapes (bad chips passing) or over-rejection (good chips failing).
    Goes in
    Packaged chips (and wafers, earlier in the flow).
    Comes out
    Known-good, binned devices ready to ship.
    Learn thisWafer test →Final test →Die-per-wafer & yield tools →

One connected system

These stages are not isolated. A MOSFET becomes a CMOS gate, gates become logic, logic is captured as RTL, RTL is placed and routed in physical design, and the result is manufactured on a wafer.

Learn paths →Engineering tools →Supply chain →SEMICON India 2026 →