IC Design Flow · Topic 6 of 9
0%
IC Design FlowLesson 6 of 9
Place & route
Positioning cells and wiring them together on the die.
What you’ll learn
- Placement and routing
- Why physical layout affects timing
- Congestion
Why it matters
Where cells sit and how wires run determines real-world speed and power.
Explanation
Placement decides where each standard cell goes on the die; routing draws the metal wires connecting them, across many layers. Both optimise timing, power, area, and routability while obeying design rules.
Long wires add delay, so placement and routing are tightly coupled to timing.
Visual explanation
Key terminology
- Placement
- Assigning physical locations to cells.
- Routing
- Drawing the interconnect wires.
- Congestion
- Too many wires needing the same area.
Example
Placing communicating blocks close together shortens critical wires and improves timing.
Common mistakes
Watch out for:
- Treating layout as cosmetic — it directly sets timing and power.
Real-world application
Modern place-and-route handles billions of objects with heavy automation.
Explore related concepts
Continue learning
Place & route
Up next
Physical design
IC Design Flow
Turning the netlist into a manufacturable layout that meets all constraints.
Continue learning →