IC Design Flow · Topic 7 of 9
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IC Design FlowLesson 7 of 9
Physical design
Turning the netlist into a manufacturable layout that meets all constraints.
What you’ll learn
- The scope of physical design
- Timing closure
- Power and clock networks
Why it matters
Physical design is where logical intent becomes a real, buildable chip.
Explanation
Physical design encompasses floorplanning, placement, clock-tree synthesis, routing, and closing timing/power/signal-integrity — iterating until every constraint is met. It's the bridge from netlist to layout.
Achieving 'timing closure' (no path too slow) across billions of gates is a central challenge.
Visual explanation
Key terminology
- Floorplan
- The high-level arrangement of major blocks.
- Timing closure
- Meeting all timing constraints.
- Clock tree
- The network distributing the clock with low skew.
Example
Clock-tree synthesis balances arrival times so flip-flops across the chip stay in sync.
Common mistakes
Watch out for:
- Assuming timing closure is automatic — it often needs many iterations.
Real-world application
Physical design teams are among the largest in a chip project.
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Physical design
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Signoff
IC Design Flow
The final checks that confirm the design is correct and manufacturable.
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