Semiconductor Fundamentals · Topic 12 of 13
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CMOS
Pairing NMOS and PMOS transistors for low-power digital logic.
What you’ll learn
- What CMOS stands for
- Why it draws almost no static power
- The CMOS inverter
Why it matters
CMOS is the dominant logic technology precisely because it wastes so little power at rest.
Explanation
CMOS (complementary MOS) uses NMOS and PMOS transistors together so that, in either steady logic state, one transistor is off. That means almost no current flows except briefly during switching.
The simplest CMOS circuit, the inverter, connects a PMOS pull-up and an NMOS pull-down; the output is always driven high or low with negligible static power.
Visual explanation
Key terminology
- Complementary
- Using both NMOS and PMOS together.
- Static power
- Power drawn when the circuit is not switching.
- Dynamic power
- Power used charging/discharging capacitance while switching.
Formula
Dynamic power scales with activity, capacitance, voltage², and clock frequency.
Example
Common mistakes
Watch out for:
- Assuming CMOS uses no power — dynamic and leakage power are very real at scale.
- Forgetting the brief short-circuit current during switching.
Real-world application
Virtually all microprocessors, memory, and logic are built in CMOS.
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CMOS
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Integrated circuit
Semiconductor Fundamentals
Millions to billions of transistors fabricated together on one chip.
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