Chip Packaging

Keeping the die and the package distinct is the key to understanding everything else. The die is the silicon; the package is the structure around it — and that structure has a consistent basic anatomy.

• Die: the piece of silicon containing the integrated circuit. It is the functional part — the transistors and wiring built during wafer fabrication.
• Package: the structure that houses and interconnects the die and connects it to the outside system. It is not functional silicon; it is the enabling shell.
• The basic stack, from the die outward: die → interconnect → package substrate → external connections → PCB/system.
• Substrate: the base inside the package that routes wiring from the die's fine pads out to coarser terminals.
• Interconnect: the wires or bumps that electrically join the die to the substrate.
• Mold compound: the encapsulant that seals and protects the die.
• Heat spreader and thermal interface material: the elements that carry heat away from the die.
• Package architecture varies by device — a sensor, a memory chip, and a processor use very different packages — but this basic set of parts and jobs recurs.

A wafer holds many identical dies laid out in a grid. Before packaging, it must be separated into those individual pieces.

• Wafer: the disc of silicon carrying many finished dies side by side.
• Die: one individual chip cut from the wafer.
• Scribe lanes: the blank 'streets' between dies, left deliberately so the wafer can be cut without damaging circuitry.
• Singulation: the act of separating the wafer into individual dies along those lanes.
• Why it is needed: each product uses one die (or a chosen few), so the wafer must be divided; only the dies that passed wafer testing are kept.

Once separated, each good die must be mechanically fastened to the package substrate before it can be connected or protected.

• Die attach bonds the die to the substrate, holding it precisely in place for the connection steps that follow.
• The attach must be mechanically strong and stable over temperature, since everything built on top depends on the die staying put.
• For many devices the attach layer also helps conduct heat from the back of the die into the package.

The die's pads must be joined electrically to the substrate. There are two broad approaches, and the difference is where and how the connections are made.

• Wire bonding: fine metal wires connect pads, usually around the edge (perimeter) of the die's top surface, out to the substrate. It is mature, flexible, and widely used.
• Flip-chip: the die is turned face-down and connected through an array of small solder bumps spread across its surface, joining directly to the substrate underneath.
• Bumps and solder-based interconnects: flip-chip uses many tiny solder bumps as the electrical (and mechanical) joints, rather than wires.
• The key difference: wire bonding connects from the die's edge or top a wire at a time, while flip-chip uses a two-dimensional array of connections across the whole die — allowing far more connections and better power and signal delivery for high-performance parts.

Chips generate heat because moving and switching charge dissipates energy. If that heat is not removed, the die gets too hot, slows down, and can fail — so every package needs a thermal path.

• The heat path is a chain: die → thermal interface material → heat spreader → heatsink/system, each stage adding thermal resistance.
• Heat flow follows temperature differences — heat moves from the hot die toward cooler surroundings, and a lower-resistance path lets more flow for a given temperature rise.
• Hotspots matter: power is not spread evenly across a die, so some regions run hotter than the average and can limit the whole chip.
• Package thermal design is about minimising thermal resistance and spreading heat, so the die stays within safe temperatures at full power.

Packages come in families defined by how they connect and how many dies they hold — not by brand. Here are the main conceptual categories.

• Traditional leaded packages: connect through metal leads around the package edge; simple and long-established for many components.
• Ball grid array (BGA): connects through a two-dimensional array of solder balls underneath the package, allowing many more connections than edge leads.
• Flip-chip packages: use flip-chip bumps between die and substrate for high connection counts and better power and signal delivery, often combined with a BGA underneath.
• System-in-package (SiP): combines multiple dies and sometimes other components into one package that behaves like a small system.
• Multi-chip packages: place several dies together in one package (side by side or stacked) so they work closely as a unit.

Testing happens more than once, because catching a bad die or package early avoids wasting money on later steps.

• Wafer sort: each die is tested while still on the wafer, so failing dies are never packaged.
• Package-level test: the finished package is tested electrically to confirm it works after assembly.
• Burn-in: parts are run under elevated temperature and voltage for a time to weed out early-life failures before shipping.
• Electrical test: functional and parametric checks confirm the component meets its specifications.
• Reliability testing: stress tests (such as thermal cycling) confirm the package will survive years of real use.
• Why multiple stages: each step adds cost, so testing early (wafer sort) avoids packaging bad dies, and testing late (package/reliability) catches faults introduced during assembly.