IC Design Flow · Topic 5 of 9
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IC Design FlowLesson 5 of 9
Verification
Proving the design does what it's supposed to — before it's built.
What you’ll learn
- Why verification dominates effort
- Simulation vs formal
- Coverage
Why it matters
A silicon bug can cost a costly re-spin, so verification often exceeds design effort.
Explanation
Verification checks the design against its specification using simulation (running testbenches), formal methods (mathematical proofs), and emulation (running RTL on special hardware). Coverage metrics track how thoroughly behaviour has been exercised.
Because fixing bugs after manufacturing is enormously expensive, verification is exhaustive.
Visual explanation
Key terminology
- Testbench
- Code that stimulates and checks a design.
- Formal verification
- Proving properties mathematically.
- Coverage
- How much of the design's behaviour has been tested.
Example
A formal tool can prove an arbiter never grants two requesters at once.
Common mistakes
Watch out for:
- Confusing 'passes my tests' with 'correct' — coverage matters.
Real-world application
Verification commonly consumes the majority of a chip project's engineering effort.
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Verification
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Place & route
IC Design Flow
Positioning cells and wiring them together on the die.
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