IC Design Flow · Topic 3 of 9
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IC Design FlowLesson 3 of 9
Logic
The Boolean gates and flip-flops that implement digital functions.
What you’ll learn
- Combinational vs sequential logic
- Standard cells
- How logic maps to CMOS
Why it matters
All digital design ultimately reduces to logic gates built from CMOS transistors.
Explanation
Combinational logic (AND, OR, NOT, XOR, …) computes outputs purely from current inputs; sequential logic (flip-flops, latches) adds memory and is clocked. Designs are built from a library of pre-characterised 'standard cells'.
Each cell is a small CMOS circuit; synthesis chooses and connects them to realise the RTL.
Visual explanation
Key terminology
- Combinational logic
- Output depends only on present inputs.
- Sequential logic
- Output depends on inputs and stored state.
- Standard cell
- A pre-designed logic gate in a library.
Example
A 2-input NAND standard cell is a four-transistor CMOS circuit.
Common mistakes
Watch out for:
- Forgetting timing — sequential logic must meet setup/hold constraints.
Real-world application
Foundries provide standard-cell libraries tuned to each process node.
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Logic
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Synthesis
IC Design Flow
Translating RTL into a gate-level netlist of standard cells.
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