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What happens to a chip after fabrication?

A semiconductor is not finished when the wafer is fabricated. Packaging connects the die to the outside world — and increasingly decides performance, power, thermal behaviour, reliability, bandwidth, form factor, and how a whole system is integrated.

First, the vocabulary

A few terms come up throughout packaging. Here they are in plain language before we use them.

Die

A single chip cut from the wafer — the bare piece of silicon carrying the circuit.

Package

The protective, connectable housing that turns a fragile die into a usable component.

Substrate

The carrier the die sits on inside the package; it fans the die's tiny connections out to larger board-level pins or balls.

Bump

A tiny solder ball on the face of a die used to connect it directly to a substrate (flip-chip), instead of using wires.

Interposer

A thin intermediate layer (often silicon) between dies and the substrate, carrying very dense wiring to link dies placed side by side (2.5D).

TSV (through-silicon via)

A vertical electrical connection etched straight through a die, letting dies be stacked and connected top-to-bottom (3D).

Chiplet

A smaller die that handles one part of a system; several chiplets are combined in one package instead of building one large chip.

Fan-out

A wafer-level technique that spreads connections beyond the die's edge without a separate substrate, for thinner, higher-density packages.

Hybrid bonding

A fine-pitch, direct copper-to-copper bond that joins dies without solder bumps, enabling very dense 3D stacking.

From wafer to finished component

  1. Wafer

    Fabrication ends with a finished wafer holding many identical dies — not yet usable chips.

    Wafer →

  2. Die

    Each individual chip on the wafer is a “die” — a bare, fragile piece of silicon.

  3. Die preparation

    The wafer is thinned and sawn into individual dies; wafer-test data marks which dies are good (known-good die).

    Dicing →Wafer test →

  4. Interconnection

    Each die's pads are connected to the package — by wire bonding (thin wires) or flip-chip (the die flipped onto solder bumps).

    Wire bonding →Flip chip →

  5. Package assembly

    The die is attached to a leadframe or substrate that routes its connections out to board-level pins or balls.

    Traditional packaging →Chip Packaging →

  6. Encapsulation

    The assembly is sealed with a moulded compound or lid, protecting it mechanically and from moisture.

    Chip Packaging →

  7. Testing

    The packaged part is tested for function, speed, and reliability (final test), then binned or discarded.

    Final test →

  8. Finished component

    The result is a packaged chip ready to be soldered onto a circuit board.

From simple to advanced

Packaging has climbed a ladder of complexity as chips demand more connections, more bandwidth, and tighter integration.

  1. Traditional (wire-bond) packaging

    What
    The die is attached to a leadframe or substrate, connected with thin bond wires, and encapsulated (packages such as QFN, QFP, BGA).
    Why
    Cheap, mature, and reliable — it covers the vast majority of chips made today.
    How
    Die attach → wire bonding → moulding → lead or solder-ball formation.
    Trade-offs
    Wires add inductance and limit how many connections and how much speed are possible.
    Where it's used
    Microcontrollers, power devices, and most consumer and industrial ICs.
    What comes next
    Flip-chip
    Learn thisTraditional packaging →Wire bonding →

  2. Flip-chip

    What
    The die is flipped face-down and connected directly to the substrate through solder bumps, with underfill added for strength.
    Why
    Far more connections and much shorter electrical paths than wires — better speed and power delivery.
    How
    Bumps are grown on the die, which is flipped and reflow-soldered to the substrate, then underfilled.
    Trade-offs
    Costlier; thermal and mechanical stress at the bumps must be managed; the substrate is more complex.
    Where it's used
    CPUs, GPUs, and other high-performance, high-pin-count chips.
    What comes next
    Wafer-level & fan-out packaging
    Learn thisFlip chip →

  3. Wafer-level & fan-out packaging

    What
    The package is built while dies are still on (or reconstituted on) a wafer; fan-out spreads connections beyond the die edge without a separate substrate.
    Why
    Thinner, smaller, higher-density packages — and it can remove the substrate cost.
    How
    Redistribution layers are formed over the die; fan-out re-embeds dies in moulding and routes connections outward.
    Trade-offs
    Warpage and yield are harder to control, and density is limited by the redistribution layers.
    Where it's used
    Mobile processors, RF front-ends, and space-constrained devices.
    What comes next
    2.5D integration
    Learn thisWafer-level packaging →

  4. 2.5D integration

    What
    Multiple dies are placed side by side on a shared silicon interposer that carries very dense wiring between them.
    Why
    Connects a large logic die to high-bandwidth memory (HBM) with far more bandwidth than a normal substrate allows.
    How
    Dies are flip-chipped onto an interposer (with TSVs) that in turn sits on the package substrate.
    Trade-offs
    The interposer is expensive and the package is large; dies still sit in a plane (no vertical logic stacking).
    Where it's used
    GPUs and AI accelerators paired with HBM, and high-end networking chips.
    What comes next
    Chiplets
    Learn this2.5D integration →HBM →

  5. Chiplets

    What
    A system is split into several smaller dies (chiplets), each possibly on a different process node, combined in one package.
    Why
    Better yield and cost than one huge die, the freedom to mix nodes, and reuse of proven blocks.
    How
    Chiplets are connected through an advanced substrate, a 2.5D interposer, or 3D stacking, using standard die-to-die interfaces.
    Trade-offs
    Die-to-die links add latency and power; interface standards and known-good-die testing add complexity.
    Where it's used
    Modern CPUs and AI accelerators.
    What comes next
    3D integration
    Learn thisChiplets →

  6. 3D integration

    What
    Dies are stacked vertically and connected top-to-bottom with through-silicon vias (TSVs) or hybrid bonding.
    Why
    The shortest possible connections and the highest density — for example, stacking memory directly on logic.
    How
    TSVs are etched through the dies and the stack is bonded, increasingly with hybrid bonding rather than microbumps.
    Trade-offs
    Heat is trapped inside the stack (a serious thermal challenge), and the process is complex and costly.
    Where it's used
    HBM stacks, stacked cache-on-logic, and leading-edge processors.
    What comes next
    Heterogeneous integration
    Learn this3D IC →

  7. Heterogeneous integration

    What
    Different kinds of dies — logic, memory, analog/RF, even optics — often from different nodes or vendors, are combined into one package as a system.
    Why
    No single process is best at everything, so the best building blocks are integrated together.
    How
    It uses the whole toolbox above — flip-chip, 2.5D interposers, chiplets, 3D stacking, hybrid bonding — as needed.
    Trade-offs
    System-level thermal, power-delivery, interface, and supply-chain complexity all rise.
    Where it's used
    Leading-edge AI/data-center parts and advanced mobile SoCs.
    Learn thisAdvanced packaging →Chiplets →

Where packaging fits

Packaging is the step after design and fabrication, and it feeds the industry that ships real products.

Design flow →Manufacturing →Supply chain →Industry (OSAT & more) →Learn paths →SEMICON India 2026 →