Packaging · Topic 11 of 14
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PackagingLesson 11 of 14
3D IC
Stacking dies vertically and connecting them through silicon.
What you’ll learn
- How 3D stacking works
- TSVs and hybrid bonding
- Benefits and challenges
Why it matters
Vertical stacking shortens connections and packs more function into a footprint.
Explanation
3D ICs stack dies on top of one another, connected vertically by through-silicon vias (TSVs) or, at the finest pitch, by hybrid bonding (direct copper-to-copper). This shortens interconnects and boosts density and bandwidth.
Heat removal and manufacturing complexity are the main challenges.
Visual explanation
Key terminology
- TSV
- Vertical via through a die connecting stacked layers.
- Hybrid bonding
- Direct fine-pitch copper-to-copper die bonding.
Example
Cache stacked directly on a CPU die via hybrid bonding cuts latency and adds capacity.
Common mistakes
Watch out for:
- Underestimating thermal challenges — stacked dies trap heat.
Real-world application
3D stacking (logic-on-logic, memory-on-logic) is a major frontier of scaling.
Explore related concepts
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3D IC
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Chiplets
Packaging
Building a system from smaller, reusable dies instead of one big die.
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