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Packaging · Topic 9 of 14

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PackagingLesson 9 of 14

Wafer-level packaging

Building the package while the dies are still on the wafer — smaller, thinner, and often without a separate substrate.

What you’ll learn

  • What wafer-level packaging (WLP) is
  • How it differs from traditional packaging
  • Fan-out WLP and its trade-offs

Why it matters

WLP enables the very small, thin packages phones and wearables need, and underpins fan-out and much of advanced packaging.

Explanation

In traditional packaging, dies are cut from the wafer first and then packaged one by one. In wafer-level packaging (WLP), the packaging steps are done while the dies are still on (or reconstituted onto) a wafer, and the wafer is diced at the very end — so many packages are built in parallel.

In the simplest “fan-in” WLP, connections stay within the die's own footprint, giving a package barely larger than the die (chip-scale). Fan-out WLP re-embeds dies in a moulded wafer and adds redistribution layers (RDL) that spread connections beyond the die edge — more connections without a separate substrate.

Advantages: smaller, thinner packages and, for fan-out, no substrate cost and shorter connections. Limitations: warpage and yield are harder to control, and the connection count is limited by the redistribution layers rather than a full substrate.

Visual explanation

diemouldingredistribution layer (RDL) — fan-outballs extend beyond the die edge
Packages built across a whole wafer, with redistribution layers spreading each die's connections beyond its edge (fan-out) before dicing.

Key terminology

RDL (redistribution layer)
A thin metal layer that re-routes a die's connections to new positions.
Fan-in / fan-out
Keeping connections within the die footprint, versus spreading them beyond it.
Chip-scale package (CSP)
A package barely larger than the die itself.

Example

Mobile processors and RF chips widely use fan-out WLP for compact, high-density packaging.

Common mistakes

Real-world application

Fan-out WLP became mainstream in smartphones and is a stepping stone toward chiplet-style integration.

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Wafer-level packaging

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2.5D integration

Packaging

Placing multiple dies side-by-side on a shared interposer.

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