Semiconductor test equipment (ATE)
Automated test equipment (ATE) that exercises a chip's functions and measures its parameters to sort good parts from bad, at both wafer and final test.
In short
Semiconductor test equipment — automated test equipment, or ATE — applies signals to a chip and measures its responses to verify it works and meets spec. It runs at wafer probe and again after packaging (final test), and sorts parts by result.
Why it matters
Only tested, known-good chips can ship. Test verifies function and performance, sorts (bins) parts by capability, and generates data that drives yield and quality — but thorough testing also adds real cost and time.
Beginner intuition
A tester is like an automated exam for the chip: it asks many questions (applies inputs) very fast and checks all the answers (outputs).
The same chip is usually tested twice — once on the wafer and once packaged — because handling and packaging can introduce new failures.
Where it fits in manufacturing
In the test step, both at wafer probe (via a prober) and at final test (via a handler), after packaging.
How it works
What goes in
- Devices to test (on-wafer via a prober, or packaged via a handler)
- A test program defining stimuli and pass/fail limits
What happens inside
- Stimulate: the tester applies electrical signals to the device.
- Measure: it captures the responses and compares them to limits.
- Bin: parts are sorted (binned) by pass/fail and by performance grade.
What comes out
- Known-good, graded parts plus rich test data for yield and quality analysis.
Major subsystems
Test head & instruments
Sources signals and measures responses.
Device interface
Connects to the device (probe card, or socket and handler).
Test program
Defines the sequence of tests and their limits.
Data system
Records results for binning and analysis.
Process parameters that matter
- Test coverage
- How thoroughly the device's functions are exercised.
- Test time
- Time per device — a direct cost driver.
- Accuracy
- Measurement precision for parametric limits.
- Parallelism
- Devices tested simultaneously.
A note on numbers
Common issues
What can go wrong:
- Insufficient coverage → bad parts shipped (test escapes)
- Over-testing → unnecessary cost and time
- Marginal limits → good parts failed or bad parts passed
- Contact or handling issues → false results
Yield implications
Test defines what ships; coverage and limits trade quality against cost, and test data is central to yield and reliability learning.
Advanced & research
Emerging and research directions, beyond today’s established practice.
- System-level test (SLT) for complex SoCs
- Higher parallelism to cut test cost
- Adaptive, data-driven test
How this connects
Related process
Related concepts
Related equipment
How this fits into manufacturing
A result is never the equipment alone. For Advanced packaging, it comes from process + equipment + material + control + metrology together.
Packaging connection
Final test is the last gate after packaging — only parts that pass here are shipped.
Packaging →Supply-chain connection
ATE, handlers, and sockets come from specialized test-equipment suppliers.
Supply chain →