3D integration
Stacking devices vertically with dense bonding.
3D integration stacks logic and memory vertically using through-silicon vias and hybrid bonding to cut interconnect distance and boost density. Research targets bonding pitch, thermal dissipation, and 3D-aware design tools.
Technologies
3D ICTSVHybrid bondingCFET
Devices
3D logic3D memory
Materials
TSV copperBonding dielectrics
Applications
AI / HPCMemory
Active research directions
- Hybrid bonding pitch scaling
- Thermal dissipation in stacks
- 3D design tools