Interconnect
Wiring the transistors together.
Learn → Understand → Explore → Calculate
At a glance
Inputs
- Wafer with completed transistors
- Dielectric and barrier films
- Copper
Outputs
- Wafer with multilevel metal interconnect
What is it?
Building the multilevel metal wiring (typically copper, with barrier and dielectric layers) that connects millions to billions of transistors into working circuits.
Why is it needed?
Transistors are useless without wiring. Modern chips stack many metal layers; as features shrink, interconnect resistance and capacitance (RC delay) increasingly limit speed and power, so materials and geometry matter enormously.
How does it work?
The dominant scheme is copper damascene: trenches and vias are etched into a dielectric, lined with a diffusion barrier, filled with copper, and then CMP removes the overburden — repeated for each metal level.
Low-κ dielectrics between wires reduce capacitance; barrier layers stop copper from diffusing into the silicon.
Critical parameters
- Line resistance
- Interconnect capacitance (RC delay)
- Via reliability
- Electromigration lifetime
Typical defects
- Voids in vias/lines
- Electromigration failures
- Barrier discontinuity
- Dielectric breakdown
Equipment involved
- Electroplating tools
- PVD/CVD for barriers and seed
- CMP polishers
Materials involved
- Copper
- Barrier metals (Ta/TaN)
- Low-κ dielectrics
Keep going
Related concepts
Related tools
Related research
- Alternative interconnect metals (Co, Ru)
- Air-gap and ultra-low-κ dielectrics