Advanced packaging & chiplets

As transistor scaling slows, performance increasingly comes from packaging: splitting a design into chiplets and integrating them on interposers (2.5D) or 3D stacks. Research covers die-to-die interconnect, thermal management, and known-good-die testing.

Active research directions

• Die-to-die interconnect standards
• Thermal management of 3D stacks
• Known-good-die test

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