Lithography
Projecting the pattern — the pacing step of Moore's Law.
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At a glance
Inputs
- Resist-coated wafer
- Photomask / reticle
- Exposure light (DUV or EUV)
Outputs
- Patterned (developed) resist stencil on the wafer
What is it?
Optically projecting each layer's pattern from a mask onto the resist-coated wafer, defining where features will be built. It is the step that sets minimum feature size.
Why is it needed?
Lithography is the pacing technology of scaling: resolution here determines how small transistors can be, and it is repeated for every patterned layer of the chip.
How does it work?
A scanner/stepper projects the mask pattern, usually demagnified, onto the resist, repeating field by field across the wafer. Resolution improves with shorter wavelength and higher numerical aperture (Rayleigh: resolution ≈ k₁·λ/NA).
Deep-ultraviolet (193 nm) light with immersion and multi-patterning served for years; extreme-ultraviolet (EUV, 13.5 nm) now enables the smallest features. Exposed resist is then developed into a stencil.
Critical parameters
- Wavelength (λ)
- Numerical aperture (NA)
- Overlay / alignment accuracy
- Depth of focus
- Dose
Typical defects
- Overlay misalignment
- Line-edge roughness
- Bridging / necking of features
- Defocus blur
Equipment involved
- DUV scanner
- EUV scanner
- Mask aligner
- Track (coat/develop)
Materials involved
- Photomask / reticle
- Developer
- Pellicle
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Related concepts
Related tools
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Related research
- High-NA EUV
- Multi-patterning and computational lithography
- Directed self-assembly